Minimal digital chaotic system
Over the past few decades, many works have been devoted to designing simple chaotic systems based on analog electronic circuits. However, the same attention is not observed in digital chaotic systems. This paper presents a design of a digital chaotic system using a digit complement. This special case of fixed-point number representation allows us to reduce the silicon area and the number of logic elements to perform the arithmetic operations.
The design presents a configurable number of bits, and it is based on the logistic map. The proposed circuit has been implemented on a reconfigurable hardware, FPGA Cyclone V, showing that the number of logic elements has been significantly reduced compared to other works in the literature.